There are numerous prior art disclosures teaching printhead designs. Typical among these prior art teachings, are designs that employ a writer interface board (WIF) to output image data and control signals such as: clock signal; token signals; latch signals; and power to the printhead board. An example of such a prior art disclosure is U.S. Pat. No.: 5,818,501 entitled Apparatus And Method For Grey Level Printing With Improved Correction of Exposure that issued to Ng et al. on Oct. 6, 1998. A problem that exists with this type of design is the number of cables that are employed in the interface between the WIF board and the printhead board, as well as the high speed clocking that is required by present day designs.
There are also numerous prior art disclosures employing center pulse width modulation (PWM) exposure techniques in order to obtain multi-level printing capability. An example of a center PWM is U.S. Pat. No. 4,750,010 entitled Circuit for Generating Center Pulse Width Modulation Waveforms and Non-Impact Printer Using Same that issued to Ayers et al. on Jun. 7, 1988. This prior art teaching is useful in providing a traditional center PWM technique, however, the methods taught within this prior art disclosure still creates transient currents (noise) when used for high speed and high quality (large bit depth) printing. Moreover, jagged graphics result using such methods.
For high speed and high quality (large bit depth) printing, a quasi-centered-PWM method has been employed by the prior art to maintain lower transient currents and thus, lower noise, and achieve centered lines/graphics resulting in less jaggedness than provided by the traditional center-PWM techniques. Additionally, quasi-centered PWM has provided superior performance associated with high speed and image quality for larger bit depth and better uniformity correction. However, this higher speed causes an increase in electromagnetic interference (EMI) which is a problem within the prior art that is addressed by the present invention.
Electrophotographic tone-reproduction processes have an inherent non-linear nature. In an LED tone-reproduction system, non-linear exposure clocks are desirable to assist in accommodating this non-linear nature. A non-linear clock is one in which the periodicity changes and is typically programmable to provide gradations of exposure more realistically related to human perception. Non-linear clocks are also used to balance LED exposure to correct for non-uniformity in illumination from printhead to printhead. Prior art designs employing non-linear clocks have a shortcoming in that they require a very high-speed exposure clock is still required resulting in EMI.
In U.S. Pat. Nos. 5,126,759 and 5,253,934 light-emitting diode (LED) printheads are described having a plurality of input lines for inputting control signals and image data to each of a plurality of driver ICs located on the printhead. In addition to power (VCC and VDD) and ground, other control signal lines include an exposure-clock signal (EXPCLK), latch signals, a token bit signal, a token bit clock signal for shifting the token bit and a token bit directional signal for determining the direction for latching data in the driver chip. As noted in the aforementioned patents, the exposure-clock signal provides non-linear clock pulses used by the driver for controlling the pulse width modulated on time of each LED in accordance with a plurality of image data bits associated with a particular pixel to be recorded. The token bit signal is used to designate a latch register which is associated with a particular LED for latching of a multi-bit data signal. As data is forwarded to a data bus in the driver, the token bit, token clock signal and token bit directional signal allow appropriate image data to be captured in a corresponding latch register. The respective data can then be printed for respective periods determined by the image data and the exposure clock pulses. In addition to the noted control signals, additional select signals are provided to the driver chips to decode various modes of operation. Among these modes are two modes that allow a multiplexed data signal to access two registers (LREF and GREF) common to every driver chip. These registers are used to bias the current output level of the drivers. In addition, there is a mode which allows a “bias monitor” output to be activated which controls monitoring of driver current in an extra channel. All of these additional functions are accessed serially in time over the same line. Since normal operation of passing image data over this same line is one of the defined modes of operation, this excludes access to these other functional modes during normal operation, i.e., when image data is passed over the line.
Traditional circuits employing differential receivers and transmitters are proving to be increasingly ineffective system design approaches as bit depth increases with corresponding increases in printing speed. Prior art designs that have their control signals, such as data-clock, token, latch, and exposure-clock, generated on a separate interface board are outdated because of the large number of conductors carrying high-speed signals resulting in bulky connectors and cables that are inherently less reliable and more costly. Moreover, these prior art designs generate undesirable effects such as EMI, signal distortions and timing skews. These problems can limit the performance of the exposure system. Accordingly, prior art designs do not result in a printhead design that is desirable in terms of modern performance requirements.
There are still many designs that employ differential receivers and transmitters for one reason or another. A specific reason that is applicable to the present invention deals with the increasing functionality of integrated circuits (ICs) and circuit boards supporting such ICs has made testing of the boards by conventional techniques ever more difficult. For this reason, the Institute of Electronic and Electrical Engineers (IEEE) has adopted a standard (1149.1) for testing circuit boards by a technique known as boundary scan. The IEEE 1149.1 proposal is substantially identical to the boundary scan architecture adopted by the Joint Test Action Group (JTAG) of Europe and North America which is described in the document JTAG Boundary Scan Architecture Version 2.0, published in March 1988. In accordance with the JTAG and IEEE boundary scan architecture individual boundary scan cells in a device (i.e. an integrated circuit ) are serially linked to establish a boundary scan register. Under the control of a test access port (TAP) controller in each device, each bit of an externally generated test vector is shifted into successive cells. Thereafter, the bit in each “output” cell (i.e., a cell whose parallel output is fed to another cell) is applied to each “input” cell (i.e., a cell whose parallel input is coupled to an output cell). The bit at the parallel input of each “input” cell is captured (i.e., retained in place of the bit originally shifted into the cell). After the bits are captured, the bits are serially shifted out of the cells and are compared to the bits in a vector expected to be produced when no faults are present. Any deviation indicates a faulty connection between cells. Prior art printhead designs have employed the JTAG and IEEE boundary scan architecture to transfer specific types of data as well as uses related to boundary scan architecture.
In summary, prior art designs that generate high-speed control signals, data, and specifically exposure-clocks, on a separate interface board are outdated because of the large number of conductors carrying high-speed signals. This results in bulky connectors and cables that are inherently less reliable and more costly. Moreover, these prior art designs generate undesirable effects such as EMI, signal distortions and timing skews. These problems can limit the performance of the exposure system. In view of the foregoing discussion it should be apparent that there remains a need within the art for a print head design that generates the exposure clock and additional control signal on the printhead itself.